Users of ADCs generally wish to see high conversion accuracy and high conversion rates. These objectives are generally opposed, and become more difficult to achieve when a user also seeks for such devices to be relatively inexpensive.
Where reduced cost, reduced power and/or greater accuracy is required, it is known to use successive approximation ADCs. A successive approximation ADC performs digital approximation of the input analog voltages that are determined on the basis of a binary search. A digital value stored in an n-bit successive approximation register (SAR) is input to a digital-to-analog converter, and a decision is made as to whether the value in the SAR represents an analog voltage that is higher or lower than the input analog value. Thus, a successive approximation converter seeking to produce an 8 bit output has to perform 8 bit trials. Therefore, due to the serial way by which the result is derived by the SAR ADCs, they are inherently slow.
One current SAR ADC technique discloses an ADC having three converters which co-operate such that each trial can determine two bits within the digital word. Whilst the performance of this device appears to be good, i.e., it reaches a conversion result much more rapidly, it suffers from several significant shortcomings. One shortcoming being, in the real world, components and systems, are noisy, whether this noise comes via the power supply lines or from self generated thermal noise. Another shortcoming is that collaborative bit trials are only possible as long as the miss-match errors between collaborative conversion engines are smaller than the resolution of the converter. This may in practice limit to ADCs to about 10 bits. One such error can come from Vt shift of comparator's MOSFETs which gives difference in non linearity (DNL) patterns. Another error can be due to settling of DAC voltage which gives DNL patterns. Yet another error can be due to settling of reference voltage which can give rise to DNL flaring and can degrade signal-to-noise ratio (SNR). Yet another error can be due to noise on DAC, reference and comparator which can increase DNL band and degrade SNR. Generally, to correct these errors redundant bit trials are used, which can take one bit trial time for each redundant bit trial. This can result in reduced speed. Further, the above SAR ADC technique does not automatically redress the errors. Furthermore, there are no provisions in this successive approximation algorithm for error corrections resulting from any of the above described errors.
Another current SAR ADC technique discloses an ADC which typically uses at least three analog-to-digital conversion engines that works in a collaborative manner during a first part of a conversion where the resulting settling errors and noise are corrected in subsequent trials. The analog-to-digital conversion engines then operate independently during a second cycle such that any settling errors and/or noise are corrected in the second cycle. However, when using more than three ADC conversion engines, this technique can require a large die area. Further, when using three ADC conversion engines, all of the above mentioned errors and noise are present in addition to requiring a large die area.
Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows.